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TM
CDP1805AC, CDP1806AC
CMOS 8-Bit Microprocessor with On-Chip RAM and Counter/Timer
Description
The CDP1805AC and CDP1806AC are functional and performance enhancements of the CDP1802 CMOS 8-bit register-oriented microprocessor series and are designed for use in general-purpose applications. The CDP1805AC hardware enhancements include a 64byte RAM and an 8-bit presettable down counter. The Counter/Timer which generates an internal interrupt request, can be programmed for use in timebase, event-counting, and pulse-duration measurement applications. The Counter/Timer underflow output can also be directed to the Q output terminal. The CDP1806AC hardware enhancements are identical to the CDP1805AC, except the CDP1806AC contains no on-chip RAM. The CDP1805AC and CDP1806AC software enhancements include 32 more instructions than the CDP1802. The 32 new software instructions add subroutine call and return capability, enhanced data transfer manipulation, Counter/Timer control, improved interrupt handling, single-instruction loop counting, and BCD arithmetic. Upwards software and hardware compatibility is maintained when substituting a CDP1805AC or CDP1806AC for other CDP1800-series microprocessors. Pinout is identical except for the replacement of VCC with ME on the CDP1805AC and the replacement of VCC with VDD on the CDP1806AC.
March 1997
Features
* Instruction Time of 3.2s, -40oC to +85oC * 123 Instructions - Upwards Software Compatible With CDP1802 * BCD Arithmetic Instructions * Low-Power IDLE Mode * Pin Compatible With CDP1802 Except for Terminal 16 * 64K-Byte Memory Address Capability * 64 Bytes of On-Chip RAM * 16 x 16 Matrix of On-Board Registers * On-Chip Crystal or RC Controlled Oscillator * 8-Bit Counter/Timer
n
Ordering Information
CDP1805AC CDP1805ACE CDP1805ACQ CDP1805ACD CDP1805ACDX CDP1806AC CDP1806ACE CDP1806ACEX CDP1806ACQ CDP1806ACD -40oC to +85oC -40oC to +85oC TEMPERATURE RANGE -40oC to +85oC PACKAGE Plastic DIP Burn-In PLCC SBDIP Burn-In N44.65 D40.6 E40.6 PKG. NO.
CDP1805AC Only
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2002. All Rights Reserved 1
File Number
1370.2
CDP1805AC, CDP1806AC Pinouts
CDP1805AC, CDP1806AC (PDIP, SBDIP) TOP VIEW
CLOCK WAIT CLEAR Q SC1 SC0 MRD BUS 7 BUS 6 1 2 3 4 5 6 7 8 9 40 VDD 38 DMA IN XTAL WAIT VDD SC1 Q 37 DMA OUT 36 INTERRUPT 35 MWR 34 TPA 33 TPB 32 MA7 31 MA6 30 MA5 29 MA4 28 MA3 27 MA2 26 MA1 25 MA0 24 EF1 23 EF2 22 EF3 21 EF4 SC0 MRD BUS 7 BUS 6 BUS 5 NC BUS 4 BUS 3 BUS 2 BUS 1 BUS 0 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 MA0 EF3 VSS EF4 EF2 EF1 NC N2 N1 N0 CLOCK NC CLEAR INTERRUPT 39 XTAL DMA - IN DMA - OUT
CDP1805AC, CDP1806AC (PLCC, PACKAGE TYPE Q) TOP VIEW
6 5 4 3 2 1 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 MWR TPA TPB MA7 MA6 NC MA5 MA4 MA3 MA2 MA1
BUS 5 10 BUS 4 11 BUS 3 12 BUS 2 13 BUS 1 14 BUS 0 15 16 N2 17 N1 18 N0 19 VSS 20
ME for CDP1805AC VDD for CDP1806AC
Schematic
ADDRESS BUS
MA0 - MA7 MRD IN CDP1851 PIO CONTROL CDP1805AC WITH RAM, COUNTER/TIMER CDP1806AC WITH COUNTER/TIMER MWR OUT BUS0 - BUS7 BUS0 - BUS7 TPA ME TPA
MA0 - MA7
MRD
MA0-MA4
CDP1833 1K BYTE ROM
CDP1824 32 BYTE RAM (USED WITH CDP1806AC ONLY) MWR
BUS0 - BUS7 (CDP1805AC ONLY)
CEO
CS
BUS0-BUS4
8-BIT DATA BUS
FIGURE 1. TYPICAL CDP1805AC, CDP1806AC SMALL MICROPROCESSOR SYSTEM
2
I/O REQUESTS MEMORY ADDRESS LINES MA7 MA5 MA3 MA1 MA6 MA4 MA2 MA0 CLEAR WAIT EF1 EF3 EF2 EF4 DMA OUT DMA IN INT I/O FLAGS CONTROL
ME FOR CDP1805AC VDD FOR CDP1806AC MUX 64-BYTE RAM CONTROL AND TIMING LOGIC CLOCK LOGIC
CDP1805AC ONLY
CLOCK
COUNTER HOLDING REGISTER (CH) MODE CONTROL CLK INTERRUPT LOGIC A (16) ALU DF (1) R(0).1 R(0).0 R(1).1 R(1).0 R(2).1 R(2).0 R(9).1 R(9).0 R(A).1 R(A).0 R(E).1 R(E).0 R(F).1 R(F).0 INCR/ DECR REGISTER ARRAY R EF1 EF2 TPA
8-BIT COUNTER/TIMER
/ 32
TC INSTRUCTION DECODE
XTAL SCO STATE CODES SCI Q LOGIC TPA TPB SYSTEM TIMING MWR MRD
CDP1805AC, CDP1806AC
FIGURE 2. BLOCK DIAGRAM FOR CDP1805AC AND CDP1806AC
3
B (8) D (8) LATCH AND DECODE 8-BIT BIDIRECTIONAL DATA BUS
BUS 0 BUS 1 BUS 2 BUS 3 BUS 4 BUS 5 BUS 6 BUS 7
X (4)
T (8)
P (4)
I (4)
N (4)
N0 N1 N2
I/O COMMANDS
CDP1805AC, CDP1806AC
Absolute Maximum Ratings
DC Supply Voltage Range, (VDD) (All Voltages Referenced to VSS Terminal). . . . . . . . . -0.5V to +7V Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to VDD +0.5V DC Input Current, any One Input . . . . . . . . . . . . . . . . . . . . . . . . . 10mA
Thermal Information
Thermal Resistance (Typical, Note 2) JA (oC/W) JC (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . 50 N/A PLCC Package . . . . . . . . . . . . . . . . . . 46 N/A SBDIP Package. . . . . . . . . . . . . . . . . . 55 15 Device Dissipation Per Output Transistor TA = Full Package Temperature Range . . . . . . . . . . . . . . 100mW Operating Temperature Range (TA) Package Type D . . . . . . . . . . . . . . . . . . . . . . . . .-55oC to +125oC Package Type E and Q . . . . . . . . . . . . . . . . . . . . .-40oC to +85oC Storage Temperature Range (TSTG). . . . . . . . . . . .-65oC to +150oC Lead Temperature (During Soldering) At Distance 1/16 1/32in (1.59 0.79mm) from case for 10s Max . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +265oC Printed Circuit Board Mount: 57mm x 57mm Minimum Area x 1.6mm Thick G10 Epoxy Glass, or Equivalent.
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Recommended Operating Conditions
TA = Full-Package Temperature Range. For maximum reliability, operating conditions
should be selected so that operation is always within the following ranges. TEST CONDITIONS VDD (V) 5 CDP1805ACD, CDP1805ACE CDP1806ACD, CDP1806ACE MIN 4 VSS 3.2 MAX 6.5 VDD UNITS V V s
PARAMETER DC Operating Voltage Range Input Voltage Range Minimum Instruction Time (Note 1) (fCL = 5MHz) Maximum DMA Transfer Rate Maximum Clock Input Frequency, Load Capacitance (CL) = 50pF Maximum External Counter/Timer Clock Input Frequency to EF1, EF2 NOTES:
5 5
DC
0.625 5
Mbyte/s MHz
5
DC
2
MHz
1. Equals 2 machine cycles - one Fetch and one Execute operation for all instructions except Long Branch, Long Skip, NOP, and "68" family instructions, which are more than two cycles. 2. JA is measured with the component mounted on an evaluation PC board in free air.
Static Electrical Specifications
at TA = -40oC to +85oC, VDD 5%, Except as Noted CDP1805ACD, CDP1805ACE CDP1806ACD, CDP1806ACE VO (V) 0.4 0.4 4.6 4.6 VIN (V) 0, 5 0, 5 5 0, 5 0 0, 5 0, 5 VDD (V) 5 5 5 5 5 5 5 (NOTE 3) TYP 50 4 0.4 -4 -0.2 0 5
PARAMETER Quiescent Device Current, IDD Output Low Drive (Sink) Current, (Except XTAL), IOL XTAL Output, IOL Output High Drive (Source) Current (Except XTAL, IOH XTAL, IOH Output Voltage Low Level, VOL Output Voltage High Level, VOH
MIN 1.6 0.2 -1.6 -0.1 4.9
MAX 200 0.1 -
UNITS A mA mA mA mA V V
4
CDP1805AC, CDP1806AC
Static Electrical Specifications
at TA = -40oC to +85oC, VDD 5%, Except as Noted (Continued) CDP1805ACD, CDP1805ACE CDP1806ACD, CDP1806ACE VO (V) 0.5, 4.5 0.5, 4.5 VIN (V) VDD (V) 5 5 (NOTE 3) TYP -
PARAMETER Input Low Voltage (BUS0 - BUS7, ME), VIL Input High Voltage (BUS0 - BUS7, ME), VIH Schmitt Trigger Input Voltage (Except BUS0 - BUS7, ME) Positive Trigger Threshold, VP Negative Trigger Threshold, VN Hysteresis, VH Input Leakage Current, IIN Three-State Output Leakage Current, IOUT Input Capacitance, CIN Output Capacitance, COUT Total Power Dissipation (Note 4) Run Idle "00" at M (0000) Minimum Data Retention Voltage, VDR Data Retention Current, IDR NOTES: 3. Typical values are for TA = +25oC and nominal VDD. 4. External clock: f = 5MHz, t R, t F = 10ns; C L = 50pF.
MIN 3.5
MAX 1.5 -
UNITS V V
0.5, 4.5 0.5, 4.5 0.5, 4.5 0, 5 -
0, 5 0, 5 -
5 5 5 5 5 -
2.2 0.9 0.3 -
2.9 1.9 0.9 0.1 0.2 5 10
3.6 2.8 1.6 5 5 7.5 15
V V V A A pF pF
-
VDD = VDR VDD = 2.4
5 5
-
35 12 2 25
50 18 2.4 100
mW mW V A
Dynamic Electrical Specifications
at TA = -40o to +85oC; C L = 50pF; Input t R, t F = 10ns; Input Pulse Levels = 0.1V to V DD -0.1V; V DD = 5V, 5%. CDP1805AC CDP1806AC (NOTE 5) TYP
PARAMETER Propagation Delay Times Clock to TPA, TPB, tPLH, tPHL Clock-to-Memory High-Address Byte, tPLH, tPHL Clock-to-Memory Low-Address Byte, tPLH, tPHL Clock to MRD, tPLH, tPHL Clock to MWR, tPLH, tPHL (See Note 5) Clock to (CPU DATA to BUS), tPLH, tPHL Clock to State Code, tPLH, tPHL Clock to Q, tPLH, tPHL Clock to N, tPLH, tPHL Clock to Internal RAM Data to BUS, tPLH, tPHL
MAX
UNITS
150 325 275 200 150 375 225 250 250 420
275 550 450 325 275 625 400 425 425 650
ns ns ns ns ns ns ns ns ns ns
5
CDP1805AC, CDP1806AC
Dynamic Electrical Specifications
at TA = -40o to +85oC; C L = 50pF; Input t R, t F = 10ns; Input Pulse Levels = 0.1V to V DD -0.1V; V DD = 5V, 5%. (Continued) CDP1805AC CDP1806AC (NOTE 5) TYP
PARAMETER Minimum Set-Up And Hold Times (Note 2) Data Bus Input Set-Up, tSU Data Bus Input Hold, tH DMA Set-Up, tSU DMA Hold, tH ME Set-Up, t ME Hold, tH Interrupt Set-Up, tSU Interrupt Hold, tH WAIT Set-Up, tSU EF1-4 Set-Up, tSU EF1 -4 Hold, tH Minimum Pulse Width Times (Note 6) CLEAR Pulse Width, tWL CLOCK Pulse Width, tW NOTES: 5. Typical values are for TA = 25o C and nominal VDD.
SU
MAX
UNITS
-100 125 -75 100 125 0 -100 100 20 -125 175
0 225 0 175 320 50 0 175 50 0 300
ns ns ns ns ns ns ns ns ns ns ns
100 75
175 100
ns ns
6. Maximum limits of minimum characteristics are the values above which all devices function.
Timing Specifications
as a function of T (T = 1/fCLOCK) at TA = -40 to +85oC, VDD = 5V, 15% CDP1805AC, CDP1806AC (NOTE 7) MAX
PARAMETER High-Order Memory-Address Byte Set-Up to TPA MRD to TPA Time, tSU Time, tSU
TYP
UNITS
2T-275 T/2 -100
2T -175 T/2 -75
ns ns
High-Order Memory-Address Byte Hold after TPA Time, tH Low-Order Memory-Address Byte Hold after WR Time, tH CPU Data to Bus Hold after WR Time, tH Required Memory Access Time, tACC Address to Data NOTE: 7. Typical values are for TA = +25oC and nominal VDD. 4.5T -440 4.5T -330 ns T +110 T +150 ns T +180 T +240 ns T/2 +75 T/2 +100 ns
6
CDP1805AC, CDP1806AC Timing Waveforms For Possible Operating Modes
INTERNAL RAM READ CYCLE
INTERNAL RAM WRITE CYCLE
00 CLOCK 01 TPA TPB MEMORY ADDRESS MRD
10 11
20 21
30 31
40 41
50 51
60 61
70 71
00 01
10 11
20 21
30 31
40 41
50 51
60 61
70 71
HIGH BYTE
LOW BYTE
HIGH BYTE
LOW BYTE
MWR
ME IN VALID DATA FROM MEMORY DATA BUS VALID DATA FROM CPU
NOTE: 8. ME has a minimum setup and hold time with respect to the beginning of clock 70. For a memory read operation, RAM data will appear on the data bus during the time ME is active after clock 31. The time shown can be longer, if for instance, a DMA out operation is performed on internal RAM data, to allow data enough time to be latched into an external device. The internal RAM is automatically deselected at the end of clock 71 independent of ME. For CDP1805AC only. FIGURE 3. INTERNAL MEMORY OPERATION TIMING WAVEFORMS
EXTERNAL MEMORY READ CYCLE 00 CLOCK 01 TPA TPB MEMORY ADDRESS MRD HIGH BYTE LOW BYTE 11 21 31 41 51 61 71 01 10 20 30 40 50 60 70 00
EXTERNAL MEMORY WRITE CYCLE 10 11 20 21 30 31 40 41 50 51 60 61 70 71
HIGH BYTE
LOW BYTE
MWR ME IN (HIGH) DATA BUS DATA LATCHED IN CPU VALID DATA FROM CPU
NOTE:
For CDP1805AC only.
FIGURE 4. EXTERNAL MEMORY OPERATION TIMING WAVEFORMS
7
CDP1805AC, CDP1806AC
0 01 10 tPLH TPA tPLH, tPHL tSU tPLH, tPHL tPLH
HIGH ORDER ADDRESS BYTE
tW CLOCK 00
1 11 20
2 21 30
3 31 40
4 41 50
5 51 60
6 61 70
7 71 00
0 01
tPHL
tPLH
tPHL
TPB MEMORY ADDRESS MRD (MEMORY READ CYCLE) MWR (MEMORY WRITE CYCLE) ME (MEMORY ENABLE) EMS (EXTERNAL MEMORY SELECT)
tH LOW ORDER ADDRESS BYTE tH tPHL
tSU tPHL tPLH tPHL tSU tH
tSU IS ALLOWABLE INTERNAL RAM ACCESS TIME tPHL tPLH, tPHL
tPLH
tH
DATA FROM CPU TO BUS tPLH tPHL tPLH, tPHL tPLH, tPHL tPLH, tPLH
DATA FROM INTERNAL MEMORY TO BUS (ME = LOW)
STATE CODES
Q N0, N1, N2 (I/O EXECUTION CYCLE) DATA FROM BUS TO CPU DMA REQUEST tPLH
tPLH, tPHL tPHL DATA LATCHED IN CPU tSU tH DMA SAMPLED (S1, S2, S3) INTERRUPT SAMPLED (S1, S2) tSU tH
INTERRUPT REQUEST
tSU
tH
FLAG LINES SAMPLED END OF S0 EF1 - EF4 tSU WAIT tWL CLEAR tH tSU tH tSU tH
NOTES:
This Timing Diagram is used to show signal relationships only, and does not represent any specific machine cycle. All measurements are referenced to 50% point of the wave forms. Shaded areas indicate "don't care" or undefined state. Multiple transitions may occur during this period. For the run (RAM only) mode only. For the run (RAM/ROM) mode only.
FIGURE 5. TIMING WAVEFORMS
8
CDP1805AC, CDP1806AC Enhanced CDP1805AC and CDP1806AC Operation
Timing Timing for the CDP1805AC and CDP1806AC is the same as the CDP1802 microprocessor series, with the following exceptions: * 4.5 Clock Cycles Are Provided for Memory Access Instead of 5. * Q Changes 1/2 Clock Cycle Earlier During the SEQ and REQ Instructions. * Flag Lines (EF1-EF4) Are Sampled at the End of the S0 Cycle Instead of at the Beginning of the S1 Cycle. * Pause Can Only Occur on the Low-To-High Transition of Either TPA or TPB, Instead of any Negative Clock Transition. Special Features Schmitt triggers are provided on all inputs, except ME and BUS 0-BUS 7, for maximum immunity from noise and slow signal transitions. A Schmitt Trigger in the oscillator section allows operation with an RC or crystal. The CDP1802 Series LOAD mode is not retained. This mode (WAIT, CLEAR = 0) is not allowed on the CDP1805AC and CDP1806AC. A low power mode is provided, which is initiated via the IDLE instruction. In this mode all external signals, except the oscillator, are stopped on the low-to-high transition of TPB. All outputs remain in their previous states, MRD is set to a logic "1", and the data bus floats. The IDLE mode is exited by a DMA or INT condition. The INT includes both external interrupts and interrupts generated by the Counter/Timer. The only restrictions are that the Timer mode, which uses the TPA / 32 clock source, and the underflow condition of the Pulse Width Measurement modes are not available to exit the IDLE mode. MRD = VDD: Input data from I/O to CPU and memory. MRD = VSS: Output data from Memory to I/O. EF1 to EF4 (4 Flags) These inputs enable the I/O controllers to transfer status information to the processor. The levels can be tested by the conditional branch instructions. They can be used in conjunction with the INTERRUPT request line to establish interrupt priorities. The flag(s) are sampled at the end of every S0 cycle. EF1 and EF2 are also used for event counting and pulse width measurement in conjunction with the Counter/Timer. INTERRUPT, DMA-IN, DMA-OUT (3 I/O Requests) DMA-lN and DMA-OUT are sampled during TPB every S1, S2, and S3 cycle. INTERRUPT is sampled during TPB every S1 and S2 cycle. Interrupt Action - X and P are stored in T after executing current instruction; designator X is set to 2; designator P is set to 1; interrupt enable (MIE) is reset to 0 (inhibit); and instruction execution is resumed. The interrupt action requires one machine cycle (S3). DMA Action - Finish executing current instruction; R(0) points to memory area for data transfer; data is loaded into or read out of memory; and R(0) is incremented.
NOTE: In the event of concurrent DMA and INTERRUPT requests, DMA-IN has priority followed by DMA-OUT and then INTERRUPT. (The interrupt request is not internally latched and must be held true after DMA).
SC0, SC1, (2 State Code Lines) These outputs indicate that the CPU is: 1) fetching an instruction, or 2) executing an instruction, or 3) processing a DMA request, or 4) acknowledging an interrupt request. The levels of state code are tabulated below. All states are valid at TPA.
STATE CODE LINES STATE TYPE S0 (Fetch) SC1 L L H H SC0 L H L H
Signal Descriptions
Bus 0 to Bus 7 (Data Bus) 8-Bit bidirectional DATA BUS lines. These lines are used for transferring data between the memory, the microprocessor, and I/O devices. N0 to N2 (I/O) Lines Activated by an I/O instruction to signal the I/O control logic of a data transfer between memory and I/O interface. These lines can be used to issue command codes or device selection codes to the I/O devices. The N-bits are low at all times except when an I/O instruction is being executed. During this time their state is the same as the corresponding bits in the N Register. The direction of data flow is defined in the I/O instruction by bit N3 (internally) and is indicated by the level of the MRD Signal:
S1 (Execute) S2 (DMA) S3 (Interrupt) NOTE: H = VDD, L = VSS.
TPA, TPB (2 Timing Pulses) Positive pulses that occurrence in each machine cycle (TPB follows TPA). They are used by I/O controllers to interpret codes and to time interaction with the data bus. The trailing edge of TPA is used by the memory system to latch the highorder byte of the multiplexed 16-bit memory address.
9
CDP1805AC, CDP1806AC
MA0 to MA7 (8 Memory Address Lines) In each cycle, the higher-order byte of a 16-bit memory address appears on the memory address lines MA0-7 first. Those bits required by the memory system can be strobed into external address latches by timing pulse TPA. The loworder byte of the 16-bit address appears on the address lines 1/2 clock after the termination of TPA. MWR (Write Pulse) A negative pulse appearing in a memory-write cycle, after the address lines have stabilized. MRD (Read Level) A low level on MRD indicates a memory read cycle. It can be used to control three-state outputs from the addressed memory and to indicate the direction of data transfer during an I/O instruction. Q Single bit output from the CPU which can be set or reset, under program control. During SEQ and REQ instruction execution, Q is set or reset between the trailing edge of TPA and the leading edge of TPB. The Q line can also be controlled by the Counter/Timer underflow via the Enable Toggle Q instruction. The Enable Toggle Q command connects the Q-line flip-flop to the output of the counter, such that each time the counter decrements from 01 to its next value, the Q line changes state. This command is cleared by a LOAD COUNTER (LDC) instruction with the Counter/Timer stopped, a CPU reset, or a BRANCH COUNTER INTERRUPT (BCl) instruction with the counter interrupt flip-flop set. Clock Input for externally generated single-phase clock. The maximum clock frequency is 5MHz at VDD = 5V. The clock is counted down internally to 8 clock pulses per machine cycle. XTAL Connection to be used with clock input terminal, for an external crystal, if the on-chip oscillator is utilized. WAIT, CLEAR (2 Control Lines) Provide four control modes as listed in the following truth table:
CLEAR L L H H WAIT L H L H MODE Not Allowed Reset Pause Run
ME (Memory Enable CDP1805AC Only) This active low input is used to select or deselect the internal RAM. It must be active prior to clock 70 for an internal RAM access to take place. Internal RAM data will appear on the data bus during the time that ME is active (after clock 31). Thus, if this data is to be latched into an external device (i.e., during an OUTPUT instruction or DMA OUT cycle), ME should be wide enough to provide enough time for valid data to be latched. The internal RAM is automatically deselected after clock 71. ME is ineffective when MRD * MWR = 1. The internal RAM is not internally mask-decoded. Decoding of the starting address is performed externally, and may reside in any 64-byte block of memory. VDD (CDP1806AC Only) This input replaces the ME signal of the CDP1805AC and must be connected to the positive power supply. VDD, VSS, (Power Levels) VSS is the most negative supply voltage terminal and is normally connected to ground. VDD is the positive supply voltage terminal. All outputs swing from VSS to VDD. The recommended input voltage swing is from VSS to VDD.
Architecture
Figure 2 shows a block diagram of the CDP1805AC and CDP1806AC. The principal feature of this system is a register array (R) consisting of sixteen 16-bit scratchpad registers. Individual registers in the array (R) are designated (selected) by a 4-bit binary code from one of the 4-bit registers labeled N, P, and X. The contents of any register can be directed to any one of the following paths: 1. The external memory (multiplexed, higher-order byte first on to 8 memory address lines). 2. The D register (either of the two bytes can be gated to D). 3. The increment/decrement circuit where it is increased or decreased by one and stored back in the selected 16-bit register. 4. To any other 16-bit scratch pad register in the array. The four paths, depending on the nature of the instruction, may operate independently or in various combinations in the same machine cycle. Most instructions consist of two 8-clock-pulse machine cycles. The first cycle is the fetch cycle, and the second, and more if necessary, are execute cycles. During the fetch cycle the four bits in the P designator select one of the 16 registers R(P) as the current program counter. The selected register R(P) contains the address of the memory location from which the instruction is to be fetched. When the instruction is read out from the memory, the higher order 4 bits of the instruction byte are loaded into the register and the lower order 4 bits into the N register. The content of the program counter is automatically incremented by one so that R(P) is now "pointing" to the next byte in the memory.
10
CDP1805AC, CDP1806AC
The X designator selects one of the 16 registers R(X) to "point" to the memory for an operand (or data) in certain ALU or I/O operations. The N designator can perform the following five functions depending on the type of instruction fetched: 1. Designate one of the 16 registers in R to be acted upon during register operations. 2. Indicate to the I/O devices a command code or deviceselection code for peripherals. 3. Indicate the specific operation to be executed during the ALU instructions, types of tests to be performed during the Branch instructions, or the specific operation required in a class of miscellaneous instructions. 4. Indicate the value to be loaded into P to designate a new register to be used as the program counter R(P). 5. Indicate the value to be loaded into X to designate a new register to be used as data pointer R(X). The registers in R can be assigned by a programmer in three different ways as program counters, as data pointers, or as scratchpad locations (data registers) to hold two bytes of data. Program Counters Any register can be the main program counter; the address of the selected register is held in the P designator. Other registers in R can be used as subroutine program counters. By a single instruction the contents of the P register can be changed to effect a "call" to subroutine. When interrupts are being serviced, register R(1) is used as the program counter for the user's interrupt servicing routine. After reset, and during a DMA operation, R(0) is used as the program counter. At all other times the register designated as program counter is at the discretion of the user. Data Pointers The registers in R may be used as data pointers to indicate a location in memory. The register designated by X (i.e., R(X)) points to memory for the following instructions (see Table 1): 1. ALU operations. 2. Output instructions. 3. Input instructions. 4. Register to memory transfer. 5. Memory to register transfer. 6. Interrupt and subroutine handling. The register designated by N (i.e., R(N)) points to memory for the "load D from memory" instructions ON and 4N and the "Store D" instruction 5N. The register designated by P (i.e., the program counter) is used as the data pointer for ALU instructions F8-FD, FF, 7C, 7D, 7F, and the RLDl instruction 68CN. During these instruction executions, the operation is referred to as "data immediate". Another important use of R as a data pointer supports the built-in Direct-Memory-Access (DMA) function. When a DMA-ln or DMA-Out request is received, one machine cycle is "stolen". This operation occurs at the end of the execute machine cycle in the current instruction. Register R(0) is always used as the data pointer during the DMA operation. The data is read from (DMA-Out) or written into (DMA-ln) the memory location pointed to by the R(0) register. At the end of the transfer, R(0) is incremented by one so that the processor is ready to act upon the next DMA byte transfer request. This feature in the CDP1805AC and CDP1806AC architecture saves a substantial amount of logic when fast exchanges of blocks of data are required, such as with magnetic discs or during CRT-display-refresh cycles. Data Registers When registers in R are used to store bytes of data, instructions are provided which allow D to receive from or write into either the higher-order- or lower-order-byte portions of the register designated by N. By this mechanism (together with loading by data immediate) program pointer and data pointer designations are initialized. Also, this technique allows scratchpad registers in R to be used to hold general data. By employing increment or decrement instructions, such registers may be used as loop counters. The new RLDl, RLXA, RSXD, and RNX instructions also allow loading, storing, and exchanging the full 16-Bit contents of the R registers without affecting the D register. The new DBNZ instruction allows decrementing and branching-on-not-zero of any 16-Bit R register also without affecting the D register. The Q Flip-Flop An internal flip-flop, Q, can be set or reset by instruction and can be sensed by conditional branch instructions. It can also be driven by the underflow output of the counter/timer The output of Q is also available as a microprocessor output.
REGISTER SUMMARY D DF B R P X N I T Q CNTR CH MIE ClE XlE ClL 8 Bits 1-Bit 8 Bits 16 Bits 4 Bits 4 Bits 4 Bits 4 Bits 8 Bits 1-Bit 8-Bits 8 Bits 1-Bit 1-Bit 1-Bit 1-Bit Data Register (Accumulator) Data Flag (ALU Carry) Auxiliary Holding Register 1 of 16 Scratch and Registers Designates which Register is Program Counter Designates which Register is Data Pointer Holds Low-Order Instr. Digit Holds High-Order Instr. Digit Holds old X, P after Interrupt (X is high nibble) Output Flip-Flop Counter/Timer Holds Counter Jam Value Master Interrupt Enable Counter Interrupt Enable External Interrupt Enable Counter Interrupt Latch
11
CDP1805AC, CDP1806AC
Interrupt Servicing Register R(1) is always used as the program counter whenever interrupt servicing is initialized. When an interrupt request occurs and the interrupt is allowed by the program (again, nothing takes place until the completion of the current instruction), the contents of the X and P registers are stored in the temporary Register T, and X and P are set to new values; hex digit 2 in X and hex digit 1 in P. Master Interrupt Enable is automatically deactivated to inhibit further interrupts. The user's interrupt routine is now in control; the contents of T may be saved by means of a single SAV instruction (78) in the memory location pointed to by R(X) or the contents of T, D, and DF may be saved using a single DSAV instruction (6876). At the conclusion of the interrupt, the user's routine may restore the pre-interrupted value of X and P with either a RET instruction (70) which permits further interrupts, or a DlS instruction (71), which disables further interrupts. Interrupt Generation and Arbitration (See Figure 6) Interrupt requests can be generated from the following sources: 1. Externally through the interrupt input (request not latched). 2. Internally due to Counter/Timer response (request is latched). a. On the transition from count (01)16 to its next value (counter underflow). b. On the mode 1. c. On the mode 2. transition of EF1 in pulse measurement transition of EF2 in pulse measurement latched counter interrupt request signal will be reset when the branch is taken, when the CPU is reset, or with a LDC instruction with the Counter stopped. Note, that exiting a counter-initiated interrupt routine without resetting the counter-interrupt latch will result in immediately reentering the interrupt routine. Counter/Timer and Controls (See Figure 7) This logic consists of a presettable 8-Bit down-counter (Modulo N type), and a conditional divide-by-32 prescaler. After counting down to (01)16the counter returns to its initial value at the next count and sets the Counter Interrupt Latch. It will continue decrementing on subsequent counts. If the counter is preset to (00)16 full 256 counts will occur. During a Load Counter instruction (LDC) if the counter was stopped with a STPC Instruction, the counter and its holding register (CH) are loaded with the value in the D Register and any previous counter interrupt is cleared. If the LDC is executed when the counter is running, the contents of the D Register are loaded into the holding register (CH) only and any previous counter interrupt is not cleared. (LDC RESETS the Counter Interrupt Latch only when the Counter is stopped). After counting down to (01)16 the next count will load the new initial value into the counter, set the Counter Interrupt Latch, and operation will continue.
For an interrupt to be serviced by the CPU, the appropriate Interrupt Enable flip-flops must be set. Thus, the External Interrupt Enable flip-flop must be set to service an external interrupt request, and the Counter Interrupt Enable flip-flop must be set to service an internal Counter/Timer interrupt request. In addition, the Master interrupt Enable flip-flop (as used in the CDP1802) must be set to service either type of request. All 3 flip-flops are initially enabled with the application of a hardware reset, and, can be selectively enabled or disabled with software: ClE, ClD instructions for the ClE flipflop; XlE, XlD instructions for the XIE flip-flop; RET, DIS instructions for the MIE flip flop. Short branch instructions on Counter Interrupt (BCI) and External Interrupt (BXl) can be placed in the user's interrupt service routine to provide a means of identifying and prioritizing the interrupt source. Note, however, that since the External Interrupt request is not latched, it must remain active until the short branch is executed if this priority arbitration scheme is used. Interrupt requests can also be polled if automatic interrupt service is not desired (MlE = 0). With the Counter Interrupt and External Interrupt short branch instructions, the branch will be taken if an interrupt request is pending, regardless of the state of any of the 3 Interrupt Enable flip-flops. The
12
CDP1805AC, CDP1806AC
RET RESET S3 DIS S MASTER Q INTERRUPT ENABLE FF R (MIE) COUNTER UNDERFLOW PULSE MODE EF1 PULSE MODE EF2 BCI CIE RESET CID S COUNTER INTERRUPT ENABLE FF R Q (CIE) RESET LDC * COUNTER STOPPED R S COUNTER INTERRUPT LATCH (CIL) Q CI TO BRANCH LOGIC (BCI)
MIE
INTERRUPT EXTERNAL INT XI TO BRANCH LOGIC (BXI) REQUESTS
XIE RESET XID
S
EXTERNAL Q INTERRUPT ENABLE FF R (XIE)
FIGURE 6. INTERRUPT LOGIC CONTROL DIAGRAM
The Counter/Timer has the following five programmable modes: 1. Event Counter 1: Input to counter is connected to the EF1 terminal. The high-to-low transition decrements the counter. 2. Event Counter 2: Input to counter is connected to the EF2 terminal. The high-to-low transition decrements the counter. 3. Timer: Input to counter is from the divide by 32 prescaler clocked by TPA. The prescaler is decremented on the low-to-high transition of TPA. The divide by 32 prescaler is reset when the counter is in a mode other than the Timer mode, system RESET, or stopped by a STPC. 4. Pulse Duration Measurement 1: Input to counter connected to TPA. Each low-to-high transition of TPA decrements the counter if the input signal at EF1 terminal (gate input) is low. On the transition of EF1 to the positive state, the count is stopped, the mode is cleared, and the interrupt request latched. If the counter underflows while the input is low, interrupt will also be set, but counting will continue. 5. Pulse Duration Measurement 2: Operation is identical to Pulse Duration Measurement 1, except EF2 is used as the gate input.
The modes can be changed without affecting the stored count. Those modes which use EF1 and EF2 terminals as inputs do not exclude testing these flags for branch instructions. The Stop Counter (STPC) instruction clears the counter mode and stops counting. The STPC instruction should be executed prior to a GEC instruction, if the counter is in the Event Counter Mode 1 or 2. In addition to the five programmable modes, the Decrement Counter instruction (DTC) enables the user to count in software. In order to avoid conflict with counting done in the other modes, the instruction should be used only after the mode has been cleared by a Stop Counter instruction. The Enable Toggle Q instruction (ETQ) connects the Q-line flip-flop to the output of the counter, such that each time the counter decrements from 01 to its next value, the Q output changes state. This action is independent of the counter mode and the Interrupt Enable flip-flops. The Enable Toggle Q condition is cleared by an LDC with the Counter/Timer stopped, system Reset, or a BCl with Cl = 1.
NOTE: SEQ and REQ instructions are independent of ETQ, they can SET or RESET Q while the Counter is running.
On-Board Clock (See Figure 8, Figure 9 and Figure 10) Clock circuits may use either an external crystal or an RC network. A typical crystal oscillator circuit is shown in Figure 8. The crystal is connected between terminals 1 and 39 (CLOCK and XTAL) in parallel with a resistance, RF (1m typ). Frequency trimming capacitors, CIN and COUT, may be required at terminals 1 and 39. For additional information on crystal oscillators, see lCAN-6565.
13
CDP1805AC, CDP1806AC
STPC
STM TPA
/ 32
R COUNTER UNDERFLOW
TO INTERRUPT LATCH INH OUT 8-BIT DOWN COUNTER
SPMI EF1
Q OUTPUT C Q Q FF D Q
ETQ
LDC SCMI LOAD
EF2 SPM2
READ
DTC
SCM2
GEC
FIGURE 7. TIMER/COUNTER DIAGRAM
Because of the Schmitt Trigger input, an RC oscillator can be used as shown in Figure 9. The frequency is approximately 1/RC (see Figure 10).
10M RF R () 1M 1M CLOCK 1 39 XTAL
VDD = 5V AT 25oC
C
C
=
C C = 1
C = 0. 1 F
=
=
0 .0
1
F
10 00 pF
10 0p F
100K
pF
10K XTAL CIN 15pF 5MHz PARALLEL RESONANT CRYSTAL COUT 27pF
1
10
100
1K
10K
100K
1M
FREQUENCY (Hz)
Pin numbers refer to 40 pin DIP.
FIGURE 8. TYPICAL 5MHz CRYSTAL OSCILLATOR
FIGURE 10. NOMINAL COMPONENT VALUES AS A FUNCTION OF FREQUENCY FOR THE RC OSCILLATOR CONTROL MODES
R
CLEAR L L
WAIT L H L H
MODE Not Allowed Reset Pause Run
CLOCK 1
39 XTAL
H H
C
Pin numbers refer to 40 pin DIP.
FIGURE 9. RC NETWORK FOR OSCILLATOR
14
CDP1805AC, CDP1806AC
The function of the modes are defined as follows: Power-up Reset/Run Circuit Power-up Reset/Run can be realized with the circuit shown in Figure 11.
VDD CDP1805AC CDP1806AC RP WAIT THE RC TIME CONSTANT SHOULD BE GREATER THAN THE OSCILLATOR START-UP TIME (TYPICALLY 20ms)
Reset
The levels on the CDP1805A and CDP1806A external signal lines will asynchronously be forced by RESET to the following states: Q=0 MRD = 1 TPB = 0 SC1, SC0 = 0,1 BUS 0-7 = 0 (EXECUTE) MA0-7 = RO.1 N0, N1, N2 = 0, 0, 0 TPA = 0 MWR = 1
RX
CLEAR
Internal Changes Caused By RESET are: l, N Instruction Register is cleared to 00. XlE and CIE are set to allow interrupts following initialize. ClL is cleared (any pending counter interrupt is cleared), counter is stopped, the counter mode is cleared, and ETQ is disabled. Initialization Cycle The first machine cycle following termination of RESET is an initialization cycle which requires 9 clock pulses. During this cycle the CPU remains in S1 and the following additional changes occur: 1 MlE X, P T (The old value of X, P will be put into T. This only has meaning following an orderly Reset with power applied). X, P, RO 0 (X, P, and RO are cleared). Interrupt and DMA servicing is suppressed during the initialization cycle. The next cycle is an S0 or an S2 but never an S1 or S3.The use of a 71 instruction followed by 00 at memory locations 0000 and 0001, may be used to reset MIE so as to preclude interrupts until ready for them. Reset and Initialize Do Not Affect: D (Accumulator) DF R1, R2, R3, R4, R5, R6, R7, R8, R9, FA, RB, RC, RD, RE, RF CH (Counter Holding Register) Counter (the counter is stopped but the value is unaffected)
CX
FIGURE 11. RESET/RUN DIAGRAM
Pause
Pause is a low power mode which stops the internal CPU timing generator and freezes the state of the processor. The CPU may be held in the Pause mode indefinitely. Hardware pause can occur at two points in a machine cycle, on the low-to-high transition of either TPA or TPB. A TPB pause can also be initiated by software with the execution of an IDLE instruction. In the pause mode, the oscillator continues to run but subsequent clock transitions are ignored. TPA and TPB remain at their previous state (see Figure 12). Pause is entered from RUN by dropping WAIT low. Appropriate Setup and Hold times must be met. If Pause is entered while in the event counter mode, the appropriate Flag transition will continue to decrement the counter. Hardware-initiated pause is exited to RUN by raising the Wait line high. Pause entered with an IDLE instruction requires DMA, INTERRUPT or RESET to resume execution.
Run
May be initiated from the Pause or Reset mode functions. If initiated from Pause, the CPU resumes operation at the point it left off. If paused at TPA, it will resume on the next high-to-low clock transition, while if paused at TPB, it will resume on the next low-to-high clock transition (see Figure 12). When initiated from the Reset operation, the first machine cycle following Reset is always the initialization cycle. The initialization cycle is then followed by a DMA (S2) cycle or fetch (S0) from location 0000 in memory.
Schmitt Trigger Inputs
All inputs except BUS 0-BUS 7 and ME contain a Schmitt Trigger circuit, which is especially useful on the CLEAR input as a power-up RESET (see Figure 11) and the CLOCK input (see Figure 8 and Figure 9).
15
CDP1805AC, CDP1806AC State Transitions
The CDP1805A and CDP1806A state transitions are shown in Figure 13. Each machine cycle requires the same period of time, 8 clock pulses, except the initialization cycle (INlT)
ENTER RESUME PAUSE RUN
which requires 9 clock pulses. Reset is asynchronous and can be forced at any time.
ENTER RESUME PAUSE RUN PAUSE
PAUSE CLOCK 70 71 00 01 PAUSE tPLH TPA WAIT tSU WAIT tPHL TPB tPLH 10 11 20 21 30 CLOCK 50 51 60
61
PAUSE
70
71
00
01
10
tPHL
tSU
tH
tSU
tH
tSU
NOTE: 9. Pause (in clock waveform) while represented here as one clock cycle in duration, could be infinitely long. FIGURE 12A. TPA PAUSE TIMING FIGURE 12B. TPB PAUSE TIMING FIGURE 12. PAUSE MODE TIMING WAVEFORMS
RESET PAUSE INT * DMA * RESET
S1 RESET DMA + INT
IDLE * DMA * INT FORCE S1 (LONG BRANCH, LONG SKIP, NOP, RSXD, ETC) DMA * FORCE S1 S1 EXECUTE
S1 INIT DMA * IDLE * INT * FORCE S1 FORCE S0 PRIORITY: RESET FORCE S0, S1 DMA IN DMA OUT INT INT * DMA * FORCE S1
DMA
DMA
DMA
S2 DMA DMA SO FETCH DMA * INT S3 INT
"68" FORCE S0
DMA INT * DMA
FIGURE 13. STATE TRANSITION DIAGRAM
16
CDP1805AC, CDP1806AC Instruction Set
The CDP1805AC and CDP1806AC instruction summary is given in Table 1. Hexadecimal notation is used to refer to the 4-bit binary codes. In all registers, bits are numbered from the least significant bit (LSB) to the most significant bit (MSB) starting with 0. R(W): Register designated by W, where W = N or X, or P R(W).0: Lower-order byte of R(W) R(W).1: Higher-order byte of R(W) Operation Notation M (R(N)) D; R(N) + 1 R(N) This notation means: The memory byte pointed to by R(N) is loaded into D, and R(N) is incremented by 1.
TABLE 1. INSTRUCTION SUMMARY (SEE NOTES) NO. OF MACHINE CYCLES
INSTRUCTION MEMORY REFERENCE LOAD IMMEDIATE REGISTER LOAD IMMEDIATE LOAD VIA N LOAD ADVANCE LOAD VIA X LOAD VIA X AND ADVANCE REGISTER LOAD VIA X AND ADVANCE STORE VIA N STORE VIA X AND DECREMENT REGISTER STORE VIA X AND DECREMENT REGISTER OPERATIONS INCREMENT REG N DECREMENT REG N DECREMENT REG N AND LONG BRANCH IF NOT EQUAL 0 INCREMENT REG X GET LOW REG N PUT LOW REG N GET HIGH REG N PUT HIGH REG N REGISTER N TO REGISTER X COPY LOGIC OPERATIONS (Note 19) OR OR IMMEDIATE EXCLUSIVE OR EXCLUSIVE OR IMMEDIATE AND
MNEMONIC
OP CODE
OPERATION
2 5 2 2 2 2 5 2 2 5
LDI RLDI LDN LDA LDX LDXA RLXA STR STXD RSXD
F8 68CN (Note 10) 0N 4N F0 72 686N (Note 10) 5N 73 68AN (Note 10)
M(R(P)) D; R(P) + 1 R(P) M(R(P)) R(N).1; M(R(P)) + 1 R(N).0; R(P) + 2 R(P) M(R(N)) D; FOR N NOT 0 M(R(N)) D; R(N) + 1 R(N) M(R(X)) D M(R(X)) D; R(X) + 1 R(X) M(R(X)) R(N).1; M(R(X) + 1) R(N).0; R(X)) + 2 R(X) D M(RN)) D M(R(X)); R(X) - 1 R(X) R(N).0 M(R(X)); R(N).1 M(R)(X) - 1); R(X) - 2 R (X)
2 2 5
INC DEC DBNZ
1N 2N 682N
R(N) + 1 R(N) R(N) - 1 R(N) R(N) - 1 R(N); IF R(N) NOT 0, M(R(P)) R(P).1, M(R(P) + 1) R(P).0, ELSE R(P) + 2 R(P) R(X) + 1 R(X) R(N).0 D D R(N).0 R(N).1 D D R(N).1 R(N) R(X)
2 2 2 2 2 4
IRX GLO PLO GHI PHI RNX
60 8N AN 9N BN 68BN (Note 10)
2 2 2 2 2
OR ORI XOR XRI AND
F1 F9 F3 FB F2
M(R(X)) OR D D M(R(P)) OR D D; R(P) + 1 R(P) M(R(X)) XOR D D M(R(P)) XOR D D; R(P) + 1 R(P) M(R(X)) AND D D
17
CDP1805AC, CDP1806AC
TABLE 1. INSTRUCTION SUMMARY (SEE NOTES) (Continued) NO. OF MACHINE CYCLES 2 2 2 2 2 2 2
INSTRUCTION AND IMMEDIATE SHIFT RIGHT SHIFT RIGHT WITH CARRY RING SHIFT RIGHT SHIFT LEFT SHIFT LEFT WITH CARRY RING SHIFT LEFT ARITHMETIC OPERATIONS (Note 3) ADD DECIMAL ADD ADD IMMEDIATE DECIMAL ADD IMMEDIATE ADD WITH CARRY DECIMAL ADD WITH CARRY ADD WITH CARRY, IMMEDIATE DECIMAL ADD WITH CARRY, IMMEDIATE SUBTRACT D SUBTRACT D IMMEDIATE SUBTRACT D WITH BORROW SUBTRACT D WITH BORROW, IMMEDIATE SUBTRACT MEMORY DECIMAL SUBTRACT MEMORY SUBTRACT MEMORY IMMEDIATE DECIMAL SUBTRACT MEMORY, IMMEDIATE SUBTRACT MEMORY WITH BORROW DECIMAL SUBTRACT MEMORY WITH BORROW SUBTRACT MEMORY WITH BORROW, IMMEDIATE
MNEMONIC ANI SHR SHRC RSHR SHL SHLC RSHL
OP CODE FA F6 76 (Note 11) 76 (Note 11) FE 7E (Note 11) 7E (Note 11)
OPERATION M(R(P)) AND D D; R(P) + 1 R(P) Shift D Right, LSB(D) DF, 0 MSB(D) Shift D Right, LSB(D) DF, DF MSB(D) SHIFT D RIGHT, LSB(D) DF, DF MSB(D) SHIFT D LEFT, MSB(D) DF, 0 LSB(D) SHIFT D LEFT, MSB(D) DF, DF LSB(D) SHIFT D LEFT, MSB(D) DF, DF LSB(D)
2 4 2 4 2 4 2 4
ADD DADD ADI DADI ADC DADC ADCI DACI
F4 68F4 FC 68FC 74 6874 7C 687C
M(R(X)) + D DF, D M(R(X)) + D DF, D DECIMAL ADJUST DF, D M(R(P)) + D DF, D; R(P) + 1 R(P) M(R(P)) + D DF, D; R(P) + 1 R(P) DECIMAL ADJUST DF, D M(R(X)) + D + DF DF, D M(R(X)) + D + DF DF, D DECIMAL ADJUST DF, D M(R(P)) + D + DF DF, D; R(P) + 1 R(P) M(R(P)) + D + DF DF, D; R(P) + 1 R(P), DECIMAL ADJUST DF, D M(R(X)) - D DF, D M(R(P)) - D DF, D; R(P) + 1 R(P) M(R(X)) - D - (NOT DF) DF, D M(R(P)) - D - (NOT DF) DF, D; R(P) + 1 R(P) D - M(R(X)) DF, D D - M(R(X)) DF, D; DECIMAL ADJUST DF, D D - M(R(P)) DF, D; R(P) + 1 R(P) D - M(R(P)) DF, D; R(P) + 1 R(P), DECIMAL ADJUST DF, D D - M(R(X)) - (NOT DF) DF, D D - M(R(X)) - (NOT DF) DF, D; DECIMAL ADJUST DF, D D - M(R(P)) - (NOT DF) DF, D; R(P) + 1 R(P)
2 2 2 2 2 4 2 4
SD SDI SDB SDBI SM DSM SMI DSMI
F5 FD 75 7D F7 68F7 FF 68FF
2 4 2
SMB DSMB SMBI
77 6877 7F
18
CDP1805AC, CDP1806AC
TABLE 1. INSTRUCTION SUMMARY (SEE NOTES) (Continued) NO. OF MACHINE CYCLES 4
INSTRUCTION DECIMAL SUBTRACT MEMORY WITH BORROW, IMMEDIATE
MNEMONIC DSBI
OP CODE 687F
OPERATION D - M(R(P)) - (NOT DF) DF, D R(P) + 1 R(P) DECIMAL ADJUST DF, D
BRANCH INSTRUCTIONS - SHORT BRANCH SHORT BRANCH NO SHORT BRANCH (See SKP) SHORT BRANCH IF D = 0 SHORT BRANCH IF D NOT 0 SHORT BRANCH IF DF = 1 SHORT BRANCH IF POS OR ZERO SHORT BRANCH IF EQUAL OR GREATER SHORT BRANCH IF DF = 0 SHORT BRANCH IF MINUS SHORT BRANCH IF LESS SHORT BRANCH IF Q = 1 SHORT BRANCH IF Q = 0 SHORT BRANCH IF EF1 = 1 (EF1 = VSS) SHORT BRANCH IF EF1 = 0 (EF1 = VDD) SHORT BRANCH IF EF2 = 1 (EF2 = VSS) SHORT BRANCH IF EF2 = 0 (EF2 = VDD) SHORT BRANCH IF EF3 = 1 (EF3 = VSS) SHORT BRANCH IF EF3 = 0 (EF3 = VDD) SHORT BRANCH IF EF4 = 1 (EF4 = VSS) SHORT BRANCH IF EF4 = 0 (EF4 = VDD) SHORT BRANCH ON COUNTER INTERRUPT SHORT BRANCH ON EXTERNAL INTERRUPT 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3 BR NBR BZ BNZ BDF BPZ BGE BNF BM BL BQ BNQ B1 BN1 B2 BN2 B3 BN3 B4 BN4 BCI BXI 30 38 (Note 11) 32 3A 33 (Note 11) 33 (Note 11) 33 (Note 11) 3B (Note 11) 3B (Note 11) 3B (Note 11) 31 39 34 3C 35 3D 36 3E 37 3F 683E (Note 12) 683F M(R(P)) R(P).0 R(P) + 1 R(P) IF D = 0, M(R(P)) R(P).0 ELSE R(P) + 1 R(P) IF D NOT 0, M(R(P)) R(P).0 ELSE R(P) + 1 R(P) IF DF = 1, M(R(P)) R(P).0 ELSE R(P) + 1 R(P) IF DF = 1, M(R(P)) R(P).0 ELSE R(P) + 1 R(P) IF DF = 1, M(R(P)) R(P).0, ELSE R(P) + 1 R(P) IF D = 0, M(R(P)) R(P).0, ELSE R(P) + 1 R(P) IF D = 0, M(R(P)) R(P).0, ELSE R(P) + 1 R(P) IF D = 0, M(R(P)) R(P).0, ELSE R(P) + 1 R(P) IF Q = 1, M(R(P)) R(P).0 ELSE R(P) + 1 R(P) IF Q = 0, M(R(P)) R(P).0 ELSE R(P) + 1 R(P) IF EF1 = 1, M(R(P)) R(P).0 ELSE R(P) + 1 R(P) IF EF1 = 0, M(R(P)) R(P).0 ELSE R(P) + 1 R(P) IF EF2 = 1, M(R(P)) R(P).0 ELSE R(P) + 1 R(P) IF EF2 = 0, M(R(P)) R(P).0 ELSE R(P) + 1 R(P) IF EF3 = 1, M(R(P)) R(P).0 ELSE R(P) + 1 R(P) IF EF3 = 0, M(R(P)) R(P).0 ELSE R(P) + 1 R(P) IF EF4 = 1, M(R(P)) R(P).0 ELSE R(P) + 1 R(P) IF EF4 = 0, M(R(P)) R(P).0 ELSE R(P) + 1 R(P) IF CI = 1, M(R(P)) R(P).0; 0 CI ELSE R(P) + 1 R(P) IF XI = 1, M(R(P)) R(P).0 ELSE R(P) + 1 R(P)
19
CDP1805AC, CDP1806AC
TABLE 1. INSTRUCTION SUMMARY (SEE NOTES) (Continued) NO. OF MACHINE CYCLES
INSTRUCTION
MNEMONIC
OP CODE
OPERATION
BRANCH INSTRUCTIONS - LONG BRANCH LONG BRANCH NO LONG BRANCH (See LSKP) LONG BRANCH IF D = 0 3 3 3 LBR NLBR LBZ C0 C8 (Note 11) C2 M(R(P)) R(P).1, M(R(P) + 1) R(P).0 R(P) + 2 R(P) IF D = 0, M(R(P)) R(P).1 M(R(P) + 1) R(P).0 ELSE R(P) + 2 R(P) IF D NOT 0, M(R(P)) R(P).1 M(R(P) + 1) R(P).0 ELSE R(P) + 2 R(P) IF DF = 1, M(R(P)) R(P).1 M(R(P) + 1) R(P).0 ELSE R(P) + 2 R(P) IF DF = 0, M(R(P)) R(P).1 M(R(P) + 1) R(P).0 ELSE R(P) + 2 R(P) IF Q = 1, M(R(P)) R(P).1 M(R(P) + 1) R(P).0 ELSE R(P) + 2 R(P) IF Q = 0, M(R(P)) R(P).1 M(R(P) + 1) R(P).0 ELSE R(P) + 2 R(P)
LONG BRANCH IF D NOT 0
3
LBNZ
CA
LONG BRANCH IF DF = 1
3
LBDF
C3
LONG BRANCH IF DF = 0
3
LBNF
CB
LONG BRANCH IF Q = 1
3
LBQ
C1
LONG BRANCH IF Q = 0
3
LBNQ
C9
SKIP INSTRUCTIONS SHORT SKIP (See NBR) LONG SKIP (See NLBR) LONG SKIP IF D = 0 LONG SKIP IF D NOT 0 LONG SKIP IF DF = 1 LONG SKIP IF DF = 0 LONG SKIP IF Q = 1 LONG SKIP IF Q = 0 LONG SKIP IF MIE = 1 CONTROL INSTRUCTIONS IDLE NO OPERATION SET P SET X 2 3 2 2 IDL NOP SEP SEX 00 (Note 14) C4 DN EN STOP ON TPB; WAIT FOR DMA OR INTERRUPT; BUS FLOATS CONTINUE NP NX 2 3 3 3 3 3 3 3 3 SKP LSKP LSZ LSNZ LSDF LSNF LSQ LSNQ LSIE 38 (Note 11) C8 (Note 11) CE C6 CF C7 CD C5 CC R(P) + 1 R(P) R(P) + 2 R(P) IF D = 0, R(P) + 2 R(P) ELSE CONTINUE IF D NOT 0, R(P) + 2 R(P) ELSE CONTINUE IF DF = 1, R(P) + 2 R(P) ELSE CONTINUE IF DF = 0, R(P) + 2 R(P) ELSE CONTINUE IF Q = 1, R(P) + 2 R(P) ELSE CONTINUE IF Q = 0, R(P) + 2 R(P) ELSE CONTINUE IF MIE = 1, R(P) + 2 R(P) ELSE CONTINUE
20
CDP1805AC, CDP1806AC
TABLE 1. INSTRUCTION SUMMARY (SEE NOTES) (Continued) NO. OF MACHINE CYCLES 2 2 2
INSTRUCTION SET Q RESET Q PUSH X, P TO STACK TIMER/COUNTER INSTRUCTIONS LOAD COUNTER GET COUNTER STOP COUNTER DECREMENT TIMER/COUNTER SET TIMER MODE AND START SET COUNTER MODE 1 AND START SET COUNTER MODE 2 AND START SET PULSE WIDTH MODE 1 AND START SET PULSE WIDTH MODE 2 AND START ENABLE TOGGLE Q INTERRUPT CONTROL EXTERNAL INTERRUPT ENABLE EXTERNAL INTERRUPT DISABLE COUNTER INTERRUPT ENABLE COUNTER INTERRUPT DISABLE RETURN DISABLE SAVE SAVE T, D, DF
MNEMONIC SEQ REQ MARK
OP CODE 7B 7A 79 1Q 0Q
OPERATION
(X, P) T; (X, P) M(R(2)), THEN P X; R(2) 1 R(2)
3 3 3 3 3 3 3 3 3 3
LDC GEC STPC DTC STM SCM1 SCM2 SPM1 SPM2 ETQ
6806 (Note 15) 6808 6800 6801 6807 6805 6803 6804 6802 6809 (Note 15)
CNTR STOPPED: D CH, CNTR; 0 CI. CNTR RUNNING; D CH CNTR D STOP CNTR CLOCK; 0 / 32 PRESCALER CNTR - 1 CNTR TPA / 32 CNTR EF1 CNTR CLOCK EF2 CNTR CLOCK TPA.EF1 CNTR CLOCK; STOPS COUNT EF1 TPA.EF2 CNTR CLOCK; STOPS COUNT EF2 IF CNTR = 01 * NEXT CNTR CLOCK ;QQ
3 3 3 3 2 2 2 6
XIE XID CIE CID RET DIS SAV DSAV
680A 680B 680C 680D 70 71 78 6876 (Note 10)
1 XIE 0 XIE l CIE 0 CIE M(R(X)) X, P; R(X) + 1 R(X); 1 MIE M(R(X) X, P; R(X) + 1 R(X); 0 MIE T M(R(X)) R(X) - 1 R(X), T M(R(X)), R(X) - 1 R(X), D M (R(X)), R(X) - 1 R(X), SHIFT D RIGHT WITH CARRY, D M(R(X))
INPUT-OUTPUT BYTE TRANSFER OUTPUT 1 OUTPUT 2 OUTPUT 3 OUTPUT 4 OUTPUT 5 2 2 2 2 2 OUT 1 OUT 2 OUT 3 OUT 4 OUT 5 61 62 63 64 65 M(R(X)) BUS; R(X) + 1 R(X) N LINES = 1 M(R(X)) BUS; R(X) + 1 R(X) N LINES = 2 M(R(X)) BUS; R(X) + 1 R(X) N LINES = 3 M(R(X)) BUS; R(X) + 1 R(X) N LINES = 4 M(R(X)) BUS; R(X) + 1 R(X) N LINES = 5
21
CDP1805AC, CDP1806AC
TABLE 1. INSTRUCTION SUMMARY (SEE NOTES) (Continued) NO. OF MACHINE CYCLES 2 2 2 2 2 2 2 2 2
INSTRUCTION OUTPUT 6 OUTPUT 7 INPUT 1 INPUT 2 INPUT 3 INPUT 4 INPUT 5 INPUT 6 INPUT 7 CALL AND RETURN STANDARD CALL
MNEMONIC OUT 6 OUT 7 INP 1 INP 2 INP 3 INP 4 INP 5 INP 6 INP 7
OP CODE 66 67 69 6A 6B 6C 6D 6E 6F
OPERATION M(R(X)) BUS; R(X) + 1 R(X) N LINES = 6 M(R(X)) BUS; R(X) + 1 R(X) N LINES = 7 BUS M(R(X)); BUS D N LINES = 1 BUS M(R(X)); BUS D N LINES = 2 BUS M(R(X)); BUS D N LINES = 3 BUS M(R(X)); BUS D N LINES = 4 BUS M(R(X)); BUS D N LINES = 5 BUS M(R(X)); BUS D N LINES = 6 BUS M(R(X)); BUS D N LINES = 7
10
SCAL
688N (Note 10)
R(N).0 M(R(X)); R(N).1 M(R(X) - 1); R(X) - 2 R(X); R(P) R(N); THEN M(R(N)) R(P).1; M(R(N) + 1) R(P).0; R(N) + 2 R(N) R(N) R(P); M(R(X) + 1) R(N).1; M(R(X) + 2) R(N).0; R(X) + 2 R(X)
STANDARD RETURN
8
SRET
689N (Note 10)
NOTES: 10. Previous contents of T register are destroyed during instruction execution. 11. This instruction is associated with more than one mnemonic. Each mnemonic is individually listed. 12. ETQ cleared by LDC with the Counter/Timer stopped, reset of CPU, or BCl * (Cl = 1). 13. Cl = Counter Interrupt, Xl = External Interrupt. 14. An IDLE instruction initiates an S1 cycle. All external signals, except the oscillator, are stopped on the low-to-high transition of TPB. All outputs remain in their previous states, MRD, MWR, are set to a logic `1' and the data bus floats. The processor will continue to IDLE until an I/O request (INTERRUPT, DMA-IN, or DMA-OUT) is activated. When the request is acknowledged, the IDLE cycle is terminated and the I/O request is serviced, and the normal operation is resumed. (To respond to an lNTERRUPT during an IDLE, MlE and either ClE or XlE must be enabled). 15. Long-Branch, Long-Skip and No Op instructions require three cycles to complete (1 fetch + 2 execute). Long-Branch instructions are three bytes long. The first byte specifies the condition to be tested; and the second and third byte, the branching address. The long branch instruction can: a. b. c. d. e. Branch unconditionally Test for D = 0 or D 0 Test for DF = 0 or DF = 1 Test for Q = 0 or Q = 1 Effect an unconditional no branch
If the tested condition is met, then branching takes place; the branching address bytes are loaded in the high-and-low-order bytes of the current program counter, respectively. This operation effects a branch to any memory location. If the tested condition is not met, the branching address bytes are skipped over, and the next instruction in sequence is fetched and executed. This operation is taken for the case of unconditional no branch (NLBR).
22
CDP1805AC, CDP1806AC
16. The short-branch instructions are two or three bytes long. The first byte specifies the condition to be tested, and the second specifies the branching address, except for the branches on interrupt. For those, the first two bytes specify the condition to be tested and the third byte specifies the branching address. The short branch instruction can: a. b. c. d. e. f. g. Branch unconditionally Test for D = 0 or D 0 Test for DF = 0 or DF = 1 Test for Q = 0 or Q = 1 Test the status (1 or 0) of the four EF flags Effect an unconditional no branch Test for counter or external interrupts (BCI, BXI)
If the tested condition is met, then branching takes place; the branching address byte is loaded into the low-order byte position of the current program counter. This effects a branch within the current 256-byte page of the memory, i.e., the page which holds the branching address. If the tested condition is not met, the branching address byte is skipped over, and the next instruction in sequence is fetched and executed. This same action is taken in the case of unconditional no branch (NBR). 17. The skip instructions are one byte long. There is one Unconditional Short-Skip (SKP) and eight Long-Skip instructions. The Unconditional Short-Skip instruction takes 2 cycles to complete (1 fetch + 1 execute). Its action is to skip over the byte following it. Then the next instruction in sequence is fetched and executed. This SKP instruction is identical to the unconditional No-Branch Instruction (NBR) except that the skipped-over byte is not considered part of the program. The Long-Skip instructions take three cycles to complete (1 fetch + 2 execute). They can: a. b. c. d. e. Skip unconditionally Test for D = 0 or D 0 Test for DF = 0 or DF = 1 Test for Q = 0 or Q = 1 Test for MIE = 1
If the tested condition is met, then Long Skip takes place; the current program counter is incremented twice. Thus, two bytes are skipped over and the next instruction in sequence is fetched and executed. If the tested condition is not met, then no action is taken. Execution is continued by fetching the next instruction in sequence. 18. Instruction 6800 through 68FF take a minimum of 3 machine cycles and up to a maximum of 10 machine cycles. In all cases, the first two cycles are fetches and subsequent cycles are executes. The first byte (68) of these two-byte op codes is used to generate the second fetch, the second byte is then interpreted differently than the same code without the 68 prefix. DMA and INT requests are not serviced until the end of the last execute cycle. 19. Arithmetic Operations: The arithmetic and shift operations are the only instructions that can alter the content of DF. The syntax `(NOT DF)' denotes the subtraction of the borrow. Binary Operations: After an ADD instruction DF = 1 denotes a carry has occurred. Result is greater than FF16. DF = 0 denotes a carry has not occurred. After a SUBTRACT instruction DF = 1 denotes no borrow. D is a true positive number. DF = 0 denotes a borrow. D is in two's complement form. Binary Coded Decimal Operations: After a BCD ADD instruction DF = 1 denotes a carry has occurred. Result is greater than 9910. DF = 0 denotes a carry has not occurred. After a BCD SUBTRACT instruction DF = 1 denotes no borrow. D is a true positive decimal number. 99 D M(R(X)) -88 11 D DF = 1 DF = 0 denotes a borrow. D is in ten's complement form. Example 88 -99 89 D M(R(X)) D Example
DF = 0
89 is the ten's complement of 11, which is the correct answer (with a minus value denoted by DF = 0).
23
CDP1805AC, CDP1806AC
TABLE 2. CONDITIONS ON DATA BUS AND MEMORY ADDRESS LINES DURING ALL MACHINE STATES DATA BUS 00 MEMORY ADDRESS UNDEFINED UNDEFINED RP RO RN RN RN RP RN RN RX RX RX RX RX RX RX RX RX N LINES 0
STATE S1
I
N RESET
MNEMONIC
OPERATION 0 Q, I, N, COUNTER, PRESCALER, CIL; 1 CIE, XIE X, P T THEN 0 X, P; 1 MIE, 0000 R0 MRP I, N; RP + 1 RP
MRD 1
MWR 1
S1 S0 S1 S1 S1 S1 S1 S1 S1 S1 S1 S1 S1 S1 S1 S1 S1 S1
INITIALIZE, NOT PROGRAMMER ACCESSIBLE FETCH 0 0 1 2 3 4 5 6 6 6 6 6 6 6 6 6 0 1-F 0-F 0-F 0-F 0-F 0-F 0 1 2 3 4 5 6 7 9 IDL LDN INC DEC SHORT BRANCH LDA STR IRX OUT 1 OUT 2 OUT 3 OUT 4 OUT 5 OUT 6 OUT 7 INP 1
00 (Note 20) MRP HIGH Z MRN HIGH Z HIGH Z MRP MRN D MRX MRX MRX MRX MRX MRX MRX MRX DATA FROM I/O DEVICE DATA FROM I/O DEVICE DATA FROM I/O DEVICE DATA FROM I/O DEVICE DATA FROM I/O DEVICE
1 0 1 0 1 1 0 0 1 1 0 0 0 0 0 0 0 1
1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 0
0 0 0 0 0 0 0 0 0 0 1 2 3 4 5 6 7 1
STOP AT TPB WAIT FOR DMA OR INT MRN D RN + 1 RN RN - 1 RN TAKEN: MRP RP.0 NOT TAKEN: RP + 1 RP MRN D; RN + 1 RN D MRN RX + 1 RX MRX BUS; RX + 1 RX MRX BUS; RX + 1 RX MRX BUS; RX + 1 RX MRX BUS; RX + 1 RX MRX BUS; RX + 1 RX MRX BUS; RX + 1 RX MRX BUS; RX + 1 RX BUS MRX, D
S1
6
A
INP 2
BUS MRX, D
RX
1
0
2
S1
6
B
INP 3
BUS MRX, D
RX
1
0
3
S1
6
C
INP 4
BUS MRX, D
RX
1
0
4
S1
6
D
INP 5
BUS MRX, D
RX
1
0
5
24
CDP1805AC, CDP1806AC
TABLE 2. CONDITIONS ON DATA BUS AND MEMORY ADDRESS LINES DURING ALL MACHINE STATES (Continued) DATA BUS DATA FROM I/O DEVICE DATA FROM I/O DEVICE MRX MRX MRX D MRX MRX HIGH Z MRX T T HIGH Z HIGH Z MRP MRP HIGH Z MRP RN.0 RN.1 D D MRP M(RP + 1) MRP M(RP + 1) MRP M(RP + 1) MEMORY ADDRESS RX N LINES 6
STATE S1
I 6
N E
MNEMONIC INP 6
OPERATION BUS MRX, D
MRD 1
MWR 0
S1
6
F
INP 7
BUS MRX, D
RX
1
0
7
S1 S1 S1 S1 S1 S1 S1 S1 S1 S1 S1 S1 S1 S1 S1 S1 S1 S1 S1 S1 S1#1 #2 S1#1 #2 S1#1 #2
7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 8 9 A B C C C C C C
0 1 2 3 4 5 6 7 8 9 A B C D E F 0-F 0-F 0-F 0-F 0-3, 8-B 0-3, 8-B 0-3, 8-B 0-3, 8-B 5 6
RET DIS LDXA STXD ADC SDB SHRC SMB SAV MARK REQ SEQ ADCI SDBI SHLC SMBI GLO GHI PLO PHI LONG BRANCH LONG BRANCH LONG BRANCH LONG BRANCH LONG SKIP LONG SKIP
MRX X, P; RX + 1 RX 1 MIE MRX X, P; RX + 1 RX 0 MIE MRX D; RX + 1 RX D MRX; RX - 1 RX MRX + D + DF DF, D MRX - D - DFN DF, D LSB(D) DF; DF MSB(D) D - MRX - DFN DF, D T MRX X, P T, MR2; P X R2 - 1 R2 0Q 1Q MRP + D + DF DF, D; RP + 1 MRP - D - DFN DF, D; RP + 1 MSB(D) DF; DF LSB D D - MRP - DFN DF, D; RP + 1 RN.0 D RN.1 D D RN.0 D RN.1 TAKEN: MRP B; RP + 1 RP TAKEN: B RP.1; MRP RP.0 NOT TAKEN RP + 1 RP NOT TAKEN RP + 1 RP TAKEN: RP + 1 RP TAKEN: RP + 1 RP
RX RX RX RX RX RX RX RX RX R2 RP RP RP RP RP RP RN RN RN RN RP RP + 1 RP RP + 1 RP RP + 1
0 0 0 1 0 0 1 0 1 1 1 1 0 0 1 0 1 1 1 1 0 0 0 0 0 0
1 1 1 0 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
25
CDP1805AC, CDP1806AC
TABLE 2. CONDITIONS ON DATA BUS AND MEMORY ADDRESS LINES DURING ALL MACHINE STATES (Continued) DATA BUS M(RP + 1) MRP MRP M(RP + 1) M(RP + 1) MRP M(RP + 1) NN NN MRX MRX MRX MRX MRX MRX MRX HIGH Z MRP MRP MRP MRP MRP MRP MRP HIGH Z DATA FROM I/O DEVICE MR0 HIGH Z MEMORY ADDRESS RP + 1 RP RP RP + 1 RP + 1 RP RP + 1 RN RN RX RX RX RX RX RX RX RX RP RP RP RP RP RP RP RP R0 N LINES 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
STATE #2 S1#1 S1#1 #2 S1#1 S1#1 #2 S1 S1 S1 S1 S1 S1 S1 S1 S1 S1 S1 S1 S1 S1 S1 S1 S1 S1 S2
I C C C C C C C D E F F F F F F F F F F F F F F F F DMA IN
N 7 C D E F 4 4 0-F 0-F 0 1 2 3 4 5 7 6 8 9 A B C D F E DMA IN
MNEMONIC LONG SKIP LONG SKIP LONG SKIP LONG SKIP LONG SKIP NOP NOP SEP SEX LDX OR AND XOR ADD SD SM SHR LDI ORI ANI XRI ADI SDI SMI SHL DMA IN
OPERATION TAKEN: RP + 1 RP NOT TAKEN: NO OPERATION NOT TAKEN: NO OPERATION NOT TAKEN: NO OPERATION NOT TAKEN: NO OPERATION NO OPERATION NO OPERATION NP NX MRX D MRX OR D D MRX AND D D MRX XOR D D MRX + D DF, D MRX - D DF, D D - MRX DF; D LSB(D) DF; 0 MSB(D) MRP D; RP + 1 RP MRP OR D D; RP + 1 RP MRP AND D D; RP + 1 RP MRP XOR D D; RP + 1 RP MRP + D DF, D; RP + 1 RP MRP - D DF, D; RP + 1 RP D - MRP DF, D; RP + 1 RP MSB(D) DF; 0 LSB(D) BUS MR0; R0 + 1 R0
MRD 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 1
MWR 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0
S2 S3
DMA OUT INTERRUPT
DMA OUT INTERRUPT
DMA OUT INTERRUPT
MRO BUS; R0 + 1 R0 X, P T; 0 MIE 1 P; 2 X
R0 RN
0 1
1 1
0 0
THE FOLLOWING ARE ALL LINKED INSTRUCTIONS "68" PRECEEDS ALL OP CODES, SO THERE IS A DUPLICATE FETCH S1 S1 0 0 0 1 STPC DTC STOP COUNTER CLOCK; 0 / 32 PRESCALER CNTR - 1 CNTR HIGH Z HIGH Z R0 R1 1 1 1 1 0 0
26
CDP1805AC, CDP1806AC
TABLE 2. CONDITIONS ON DATA BUS AND MEMORY ADDRESS LINES DURING ALL MACHINE STATES (Continued) DATA BUS HIGH Z HIGH Z HIGH Z HIGH Z D MEMORY ADDRESS R2 R3 R4 R5 R6 N LINES 0 0 0 0 0
STATE S1 S1 S1 S1 S1
I 0 0 0 0 0
N 2 3 4 5 6
MNEMONIC SPM2 SCM2 SPM1 SCM1 LDC
OPERATION CNTR - 1 ON EF2 AND TPA CNTR - 1 ON EF2 0 TO 1 CNTR - 1 ON EF1 AND TPA CNTR - 1 ON EF1 0 TO 1 CNTR STOPPED: D CH, CNTR; 0 CI CNTR RUNNING: D CH CNTR - 1 ON TPA / 32 CNTR D IF CNTR THRU 0: Q Q 1 XIE 0 XIE 1 CIE 0 CIE RN - 1 RN MRP B; RP + 1 RP TAKEN: B RP.1, MRP RP.0 NOT TAKEN: RP + 1 RP TAKEN: MRP RP.0; 0 CI NOT TAKEN: RP + 1 RP TAKEN: MRP RP.0 NOT TAKEN: RP + 1 RP MRX B, RX + 1 RX B T; MRX B; RX + 1 RX B, T RN.0, RN.1 MRX + D + DF DF, D DECIMAL ADJUST DF, D RX - 1 RX T MRX; RX - 1 RX D MRX; RX - 1 RX SHIFT D RIGHT WITH CARRY D MRX D - MRX - (NOT DF) DF, D DECIMAL ADJUST DF, D MRP + D + DF DF, D; RP + 1 RP DECIMAL ADJUST DF, D D - MRP - (NOT DF) DF, D; RP + 1 RP
MRD 1 1 1 1 1
MWR 1 1 1 1 1
S1 S1 S1 S1 S1 S1 S1 S1#1 #2 #3
0 0 0 0 0 0 0 2 2 2
7 8 9 A B C D 0-F 0-F 0-F
STM GEC ETQ XIE XID CIE CID DBNZ DBNZ DBNZ
HIGH Z CNTR HIGH Z HIGH Z HIGH Z HIGH Z HIGH Z HIGH Z MRP M(RP + 1)
R7 R8 R9 RA RB RC RD RN RP RP + 1
1 1 1 1 1 1 1 1 0 0
1 1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0 0 0
S1
3
E
BCI
MRP
RP
0
1
0
S1 S1#1 #2 #3 S1#1 #2 S1#1 #2 #3 #4 S1#1 #2 S1#1 #2 S1#1
3 6 6 6 7 7 7 7 7 7 7 7 7 7 7
F 0-F 0-F 0-F 4 4 6 6 6 6 7 7 C C F
BXI RLXA RLXA RLXA DADC DADC DSAV DSAV DSAV DSAV DSMB DSMB DACI DACI DSBI
MRP MRX M(RX + 1) HIGH Z MRX HIGH Z HIGH Z T D D MRX HIGH Z MRP HIGH Z MRP
RP RX RX + 1 RN RX RD RP RX - 1 RX - 2 RX - 3 RX RP RP RP + 1 RP
0 0 0 1 0 1 1 1 1 1 0 1 0 1 0
1 1 1 1 1 1 1 0 0 0 1 1 1 1 1
0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
27
CDP1805AC, CDP1806AC
TABLE 2. CONDITIONS ON DATA BUS AND MEMORY ADDRESS LINES DURING ALL MACHINE STATES (Continued) DATA BUS HIGH Z HIGH Z RN.0 RN.1 HIGH Z HIGH Z MRP M(RP + 1) HIGH Z HIGH Z HIGH Z HIGH Z M(RX + 1) M(RX + 1 HIGH Z HIGH Z RN.0 RN.1 HIGH Z HIGH Z MRP M(RP + 1) HIGH Z MRX HIGH Z MRX HIGH Z MRP HIGH Z MRP HIGH Z MEMORY ADDRESS RP + 1 RN RX RX - 1 RP RN RP RP + 1 RP RN RX RP RX + 1 RX + 2 RN RN RX RX - 1 RN RX RP RP + 1 RN RX RP RX RP RP RP + 1 RP RP + 1 N LINES 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
STATE #2 S1#1 #2 #3 #4 #5 #6 #7 #8 S1#1 #2 #3 #4 #5 #6 S1#1 #2 #3 S1#1 #2 S1#1 #2 #3 S1#1 #2 S1#1 #2 S1#1 #2 S1#1 #2 NOTE:
I 7 8 8 8 8 8 8 8 8 9 9 9 9 9 9 A A A B B C C C F F F F F F F F
N F 0-F 0-F 0-F 0-F 0-F 0-F 0-F 0-F 0-F 0-F 0-F 0-F 0-F 0-F 0-F 0-F 0-F 0-F 0-F 0-F 0-F 0-F 4 4 7 7 C C F F
MNEMONIC DSBI SCAL SCAL SCAL SCAL SCAL SCAL SCAL SCAL SRET SRET SRET SRET SRET SRET RSXD RSXD RSXD RNX RNX RLDI RLDI RLDI DADD DADD DSM DSM DADI DADI DSMI DSMI
OPERATION DECIMAL ADJUST DF, D RN.0, RN.1 T, B T MRX RX - 1 RX B MRX RX - 1 RX RP.0, RP.1 T, B B, T RN.1, RN.0 MRN B; RN + 1 RN B T; MRN B; RN + 1 RN B, T RP.0, RP.1 RN.0, RN.1 T, B RX + 1 RX B, T RP.1, RP.0 MRX B; RX + 1 RX B T; MRX B B, T RN.0, RN.1 RN.0, RN.1 T, B T MRX; RX - 1 RX B MRX; RX - 1 RX RN.0, RN.1 T, B B, T RX.1, RX.0 MRP B; RP + 1 RP B T; MRP B; RP + 1 RP B, T RN.0, RN.1; RP + 1 RP MRX + D DF; D DECIMAL ADJUST DF, D D - MRX DF, D DECIMAL ADJUST DF, D MRP + D DF, D; RP + 1 RP DECIMAL ADJUST DF, D D - MRP DF, D RP + 1 RP DECIMAL ADJUST DF, D
MRD 1 1 1 1 1 1 0 0 1 1 1 1 0 0 1 1 1 1 1 1 0 0 1 0 1 0 1 0 1 0 1
MWR 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1
20. Data bus floats for first 2-1/2 clocks of the nine clock initialization cycle; all zeros for remainder of cycle.
28
CDP1805AC, CDP1806AC
INSTRUCTION SUMMARY N 0 0 1 2 3 4 5 6 7 8 9 A B C D E F LDX OR AND XOR ADD SD SHR SM LBR LBQ LBZ LBDF NOP LSNQ LSNZ LSNF IRX RET DIS LDXA STXD OUT ADC SDB SHRC SMB BR BQ BZ BDF B1 B2 B3 B4 IDL 1 2 3 4 5 6 7 8 LDN INC DEC SKP LDA STR SAV GLO GHI PLO PHI LSKP LBNQ LBNZ SEP SEX LDI ORI ANI XRI ADI SDI SHL SMI LBNF LSIE LSQ LSZ LSDF MARK REQ SEQ INP ADCI SDBI SHLC SMBI BNQ BNZ BNF BN1 BN2 BN3 BN4 9 A B C D E F
`68' LINKED OPCODES (DOUBLE FETCH) 0 2 3 6 7 8 9 A B C F DADD DSM DADC DSAV DSMB STPC DTC SPM2 SCM2 SPM1 SCM1 LDC STM GEC DBNZ RLXA SCAL SRET RSXD RNX RLDI DADI DSMI DACI DSBI BCI BXI ETQ XIE XID CIE CID -
`68' is used as a linking OPCODE for the double fetch instructions.
29
CDP1805AC, CDP1806AC Operating and Handling Considerations
Handling All inputs and outputs of Intersil CMOS devices have a network for electrostatic protection during handling. Operating Operating Voltage During operation near the maximum supply voltage limit, care should be taken to avoid or suppress power supply turn-on and turn-off transients, power supply ripple, or ground noise; any of these conditions must not cause VDD VSS to exceed the absolute maximum rating. Input Signals To prevent damage to the input protection circuit, input signals should never be greater than VDD nor less than VSS. Input currents must not exceed 10mA even when the power supply is off. Unused Inputs A connection must be provided at every input terminal. All unused input terminals must be connected to either VDD or VSS, whichever is appropriate. Output Short Circuits Shorting of outputs to VDD or VSS may damage CMOS devices by exceeding the maximum device dissipation.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
30

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